The present invention relates to nonvolatile memories.
FIG. 1 shows a cross section of a flash memory cell 110 disclosed in U.S. Pat. No. 6,134,144 issued Oct. 17, 2000 to Lin et al. Floating gate 120, control gate 130, and select gate 140 are formed over semiconductor substrate 150. Drain 160 and source 170 are N type doped regions formed in substrate 150 adjacent to select gate 140 and floating gate 120 respectively. P type doped channel region 180 extends in substrate 150 between source 170 and drain 160. The gates 120, 130, 140 are insulated from each other and the substrate by insulating layers.
The cell is programmed by hot electron injection as the control gate 130 is held at a super high voltage of 12 V, select gate 140 is held at 1 V, drain 160 is held at 0 V, and source 170 is held at 5 to 8 V. Hot electrons are injected from channel 180 into floating gate 120 to negatively charge the floating gate.
The cell is erased by Fowler-Nordheim tunneling of electrons from floating gate 120 to source 170 as source 170 is held at 12 V and control gate 130, drain 160, and select gate 140 are at 0 V.
FIG. 2 is a circuit diagram of a flash memory array formed with the cells of FIG. 1. Each cell 110 is shown schematically as an NMOS transistor and a floating gate transistor connected in series. In each row of the array, the select gates 140 are provided by a polysilicon wordline. The wordlines of rows 0, 1, etc. are shown respectively as WL0, WL1, etc., and are also referenced as 140. In each row, control gates 130 are also provided by a polysilicon line (xe2x80x9ccontrol gate linexe2x80x9d). The control gate lines of rows 0, 1, etc. are shown as CGL0, CGL1, etc., and are also referenced as 130. Each control gate line CGLi (i=0, 1, . . . ) is in the same row xe2x80x9cixe2x80x9d as wordline WLi.
In each row, source regions 170 are formed as a diffusion line (xe2x80x9csource linexe2x80x9d) in substrate 150. Every two adjacent rows share a source line. Thus, rows 0 and 1 share source line SL0-1, rows 2 and 3 share source line SL2-3, and so on.
Metal bitlines BL0, . . . BL63, also referenced as 210, are perpendicular to the wordlines, the control gate lines, and the source lines. Each bitline is connected to drains 160 of a column of the memory cells.
Decoders (not shown) are positioned on the sides of the array to supply appropriate signals to the wordlines, the control gate lines and the source lines. Additional circuitry (not shown) supplies appropriate signals to the bitlines for the erase and program operations, and connects the bitlines to sense amplifiers (not shown) during the read operations.
The memory array is organized as a number of pages. A page contains eight rows whose source lines 170 are connected together. For example, the source lines SL0-1, SL2-3, SL4-5, SL6-7 of rows 0-7 are connected together. The eight control gate lines 130 of each page are also connected together. The individual rows are selected by activating the associated wordlines.
Connecting together the control gate lines 130 of each page reduces the size of the decoding circuitry needed to select a control gate line. However, the memory cells become more vulnerable to punch-through during programming. Suppose for example that cell 110.0 in row 0, column 0 is being programmed. Control gate line CGL0 is at 12 V, wordline WL0 is at 1 V, source line SL0-1 is at 5 to 8 V, and bitline BL0 is at 0 V. Word lines WL1, WL2, etc. are at 0 V. During programming, the unselected cell 110.1 has the following voltages on its terminals: its control gate 130 is at 12 V, source 170 at 5 to 8 V, drain 160 at 0 V, and select gate 140 at 0 V. Consequently, the voltage on source 170 is passed along channel portion 180.1 underlying the floating gate, and a 5 to 8 V potential difference appears across channel portion 180.2 underlying select gate 140. As a result, the cell may experience a high leakage current. In addition, the cell may suffer a punch-through, with a high current flowing from the drain to the source. To reduce the probability of a punch-through, one can increase the length of select gate 140, but this undesirably increases the cell size. One can also increase the doping level of channel 180, but this undesirably reduces the cell current when the cell is selected for reading or programming.
The punch-through problem is particularly dangerous for the memory cells in which the select gate is formed as a sidewall spacer because the length of the select gate can be less than one feature size (a feature size is a minimum line width obtainable with the photolithographic processes used in the memory fabrication). Two such cells sharing a source line 170 are shown in FIG. 3. The cells are manufactured as described in U.S. patent application Ser. No. 09/640,139 filed Aug. 15, 2000 by H. T. Tuan et al., entitled xe2x80x9cNonvolatile Memories and Methods of Fabricationxe2x80x9d (now U.S. Pat. No. 6,355,524), incorporated herein by reference. Briefly, insulating layer 310 is formed on a P-doped region of monocrystalline silicon substrate 150. Doped polysilicon layer 120 is formed on insulator 310. Then polysilicon 120 (the floating gate layer) is removed between different columns of the array so that the floating gates of different columns would not be connected to each other. The floating gates within each column remain connected to each other at this stage.
Insulator 320 is formed on layer 120. Doped polysilicon 130 is formed on insulator 320. Silicon nitride 330 is formed on polysilicon 130. Then layers 330, 130, 320, 120, 310 are etched to form stacks 334 extending along each row of the array. In each stack, polysilicon 130 provides a control gate line. Polysilicon 120 is removed between the rows during this etch, so the floating gates 120 become fully isolated from each other.
Insulator 340 is formed on the sidewalls of each stack 334. (Layer 340 may include thermally grown silicon dioxide and may also include silicon nitride spacers formed by conformal deposition and a maskless etch of silicon nitride.) Silicon dioxide 350 is grown on the exposed portions of substrate 150.
Conformal polysilicon layer 140 is deposited and etched anisotropically to form spacers on the sidewalls of each stack 334. The etch does not require a mask over the memory array. Then a masked etch of polysilicon 140 removes the spacers on the source line side of each stack. The spacer on the drain side of the stack provides a wordlines WLi for the corresponding row. Source lines 170 and drain regions 160 are doped at suitable steps during fabrication.
The memory cells of FIG. 3 can be individually programmed by hot electron injection from channel region 180 to the floating gate. The cells connected to the same source line 170 (a xe2x80x9csectorxe2x80x9d) can be erased together by Fowler-Nordheim tunneling from the floating gates 120 to the source line 170 or substrate 150. In one embodiment, the following voltages can be used for the memory operation:
Slashes are used in Table 1 to indicate the voltages for selected/non-selected memory rows or columns. For example, in the xe2x80x9cProgramxe2x80x9d column of Table 1, in the row xe2x80x9cDrain 160xe2x80x9d, the entry xe2x80x9c0 V/V3xe2x80x9d indicates 0 V for the selected bitline and a voltage V3 for the non-selected bitlines. Not all of the non-selected voltages are shown.
In some embodiments of the present invention, the punch-through probability is reduced by modifying the memory array. One embodiment is shown in FIG. 4. The memory array is similar to that of FIG. 2, with the source lines 170 connected together in each page of eight rows. Control gate lines 130 are also connected together, but not in the same page. For example, control gate line CGL0 in page 0 is connected to control gate line CGL8 in page 1, and can also be connected to one control gate line in each of pages 2, 3, 4, 5, 6, and 7. Control gate line CGL1 in page 0 is connected to control gate CGL9, and can also be connected to one control gate line in each of pages 2, 3, 4, 5, 6, and 7. Each control gate line CGL in page 0 can be connected to one control gate line in each of pages 1, 2, 3, 4, 5, 6, 7, and/or in some other pages. The control gate lines of the same page are not connected together. Now suppose that cell 110.0 (row 0, column 0) is selected for programming. Then cell 110.1 has both its control gate 130 and select gate 140 at 0 V, so the leakage current is smaller and the punch-through is less likely to occur. Cell 110.2 (row 8, column 0) has its control gate 130 at a high voltage, but its source 170 (line SL8-9) is at 0 V. Therefore, the source to drain voltage is 0 V, so the leakage current is 0 and the punch-through does not occur.
Other features and embodiments of the invention are described below. The invention is defined by the appended claims.